1. Field of this Invention
The present invention relates generally to bus systems in a System-On-Chip (SOC), and more particularly, to a bus system allowing simultaneous data transfers.
2. Description of Prior Art
Bus systems may allow communication between a plurality of Intellectual Property (IP) cores on a chip. Advanced High-performance Bus (AHB) systems based on an Advanced Microcontroller Bus Architecture (AMBA) protocol have been increasingly used in recent years. Thus, IP cores may be designed based on the AMBA protocol.
In order to reduce a time-to-market for IP cores, IP cores may be recycled (i.e., reused). This recycling may shorten a design time and improve reliability of chips. One example of a bus system using the above-described recycled IP cores is a Silicon Backplane (SB) micro-network based on an Open Core Protocols (OCP).
FIG. 1 illustrates a block diagram of an AHB bus system 150.
Referring to FIG. 1, the AHB bus system 150 may be based on the AMBA protocol (e.g., AMBA protocol specification 2.0). The AHB bus system 150 may include masters 100/102/104, slaves 120/122/124/126, an arbiter 110, and/or a decoder 118. The AHB bus system 150 may further include a plurality of multiplexer (MUX) circuits 112/114/116 for controlling data-flow between the masters 100/102/104 and the slaves 120/122/124/126. The MUX circuits 112/114/116 may be controlled by the arbiter 110 and/or the decoder 118.
One of the masters 100/102/104 may request bus access from the arbiter 110 to designate a connection between one of the masters 100/102/104 and one of the slaves 120/122/124/126 via the bus. After the bus connection is assigned, data may be transferred (e.g., read and/or written) between a selected one of the masters 100/102/104 and a selected one of the slaves 120/122/124/126.
For example, master 100 may request bus access from the arbiter 110 by submitting a bus-use-request HBUSREQ1 in order to write data to slave 124. The arbiter 110 may determine whether the slave 124 is available (i.e., whether another one of the masters 100/102/104 is currently communicating with the slave 124). If the slave 124 is available, the arbiter 110 may apply a bus-grant-signal HGRANT to the master 100. The arbiter 110 may control the first and second MUX circuits 112 and 114, respectively, so as to transmit data HWDATA1 from the master 100 to the slave 124. The first MUX circuit 112 may transmit an address signal HADDR and a control signal from the master 100 to the slave 124, and the second MUX circuit 114 may transmit data HWDATA from the master 100 to the slave 124. If the data is transmitted from the master 100, the slave 124 may apply a signal indicating that the data is transmitted from the master 100. When data is transmitted from the master 100, a data transmission state signal HREADY may be applied from the master 100 to the slave 124 by a third MUX circuit 116 which may be controlled by a decoder 118.
FIG. 2A illustrates a timing diagram of signals HCLK, HWDATA, and HREADY for the AHB bus system 150 of FIG. 1 when one of the masters 100/102/104 transmits data over a single cycle.
FIG. 2B illustrates a timing diagram of signals HCLK, HWDATA, and HREADY for the AHB bus system 150 of FIG. 1 when one of the masters 100/102/104 transmits data over several cycles.
Referring to FIG. 2A, when the data HWDATA from one of the masters 100/102/104 is transmitted during one cycle, the data transmission state signal HREADY from the slave 120/122/124/126 (i.e., the slave which receives the data) maintains a high state (i.e., a high logic or voltage level). In contrast, referring to FIG. 2B, when data DATA_B is transmitted from one of the masters 100/102/104 to the slave 120/122/124/126 (i.e., the slave which receives the data) during several cycles, the data transmission state signal HREADY may maintain a low state (i.e., a low logic or voltage level) until the data DATA_B is completely transmitted.
Referring to FIGS. 2A and 2B, when the data transmission state signal HREADY is in the low state, the DATA and/or DATA_B may be transmitted. However, operations beyond the single allowed data transfer may not be possible when the data transmission state signal HREADY is in the low state. Thus, if the data transmission state signal HREADY is in a low state, the AHB bus system 150 may be considered to be in a wait state (i.e., other operations must wait for data transfer to complete before continuing).
FIG. 3 illustrates a block diagram of a SB micro-network 300 based on OCP.
Referring to FIG. 3, the SB micro-network 300 may include an SB bus 302 and a plurality of agents 304. Each of the plurality of agents 304 may be connected to at least one of IP cores 310/312/314/318/320/322, each of which may be operated by a master and/or a slave. The SB bus 302 may be tree-shaped, as shown in FIG. 3, or ring-shaped. The plurality of agents 304 may connect the IP cores 310/312/314/318/320/322 to the SB bus 302.
In another method, referring to FIG. 3, the IP cores 310/312/314/318/320/322 may be classified into two types; namely, a first type may be characterized by being operated only by masters (e.g., masters 310/312) or only by slaves (e.g., slaves 318/320/322), and a second type may be characterized by being operated by at least one master and at least one slave (e.g., master 316 and slave 317), similar to an IP core based on a register.
In another method, the IP cores 310 may be based on the AMBA protocol of FIG. 3. If the master enters the wait state (i.e., the HREADY signal may be in a low state) when data is transferred in the IP core operated by both the master and the slave (i.e., similar to the second type described above), the slave may not perform any operation until the wait state is over.
In an example, if the slave is a register for setting an operation state (e.g., writing, reading, waiting, etc. . . . ) of the master 316, the setting of the register may be changed when the master 316 enters the wait state. Thus, the wait state of the master 316 may function as a wait state of the entire IP core (i.e., all operations other than the data transfer are halted within the IP core).